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sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? high speed: 12, 15, 20, 25, 35, 45, 55, and 70ns ? battery backup: 2v data retention ? high-performance, low-power cmos double-metal process ? single +5v ( +10%) power supply ? easy memory expansion with ce\ ? all inputs and outputs are ttl compatible options marking ? timing 12ns access -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45* 55ns access -55* 70ns access -70* ? package(s) ceramic dip (300 mil) c no. 106 ceramic lcc e c no. 204 ? operating temperature ranges industrial (-40 o c to +85 o c) it military (-55 o c to +125 o c) xt ? 2v data retention/low power l *electrical characteristics identical to those provided for the 35ns access devices. pin assignment (top view) available as military specifications ? smd 5962-86859 ? mil-std-883 general description the austin semiconductor sram family employs high-speed, low-power cmos designs using a four-transistor memory cell. austin semiconductor srams are fabricated using double-layer metal, double-layer polysilicon technology. for flexibility in high-speed memory applications, austin semiconductor offers chip enable (ce\) and output enable (oe\) capability. these enhancements can place the outputs in high-z for additional flexibility in system design. writing to these devices is accomplished when write enable (we\) and ce\ inputs are both low. reading is accomplished when we\ remains high and ce\ and oe\ go low. the device offers a reduced power standby mode when disabled. this allows system designs to achieve low standby power requirements. all devices operate from a single +5v power supply and all inputs and outputs are fully ttl compatible. 16k x 4 sram sram memory array for more products and information please visit our web site at www.austinsemiconductor.com 28-pin lcc (ec) 3 2 1 28 27 13 14 15 16 17 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 a6 a7 a8 a9 a10 a11 a12 a13 ce\ nc a4 a3 a2 a1 a0 dq4 dq3 dq2 dq1 we\ nc vss oe\ a5 nc nc vcc nc 24-pin dip (c) (300 mil) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 a5 a6 a7 a8 a9 a10 a11 a12 a13 ce\ oe\ vss vcc a4 a3 a2 a1 a0 nc dq4 dq3 dq2 dq1 we\
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 functional block diagram truth table row decoder 1,048,576-bit memory array i/o control v cc gnd d we\ a a a a a a a a a column decoder a a a a a a a a a a power down ce\ (lsb) (lsb) q oe\ mode oe\ ce\ we\ dq power standby x h x high-z standby read l l h q active read h l h high-z active write x l l d active
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 absolute maximum ratings* voltage on any input or dq relative to vss....-0.5v to +7.0v 1 storage temperature...................................-65 o c to +150 o c power dissipation.................................................................1w max junction temperature..................................................+175 c lead temperature (soldering 10 seconds)........................+260 o c short circuit output current...........................................20ma *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (-55 o c < t c < 125 o c; v cc = 5v +10%) capacitance 1 all voltage referenced to vss. description conditions sym min max units notes input high (logic 1) voltage v ih 2.2 vcc+0.5v v 1 input low (logic 0) voltage v il -0.5 0.8 v 1, 2 input leakage current 0v < v in < v cc il i -10 10 a output leakage current outputs disabled 0v < v out < v cc il o -10 10 a output high voltage i oh = -4.0ma v oh 2.4 v 1 output low voltage i ol = 8.0ma v ol 0.4 v 1 sym -12 -15 -20 -25 -35 units notes i cc 140 125 110 100 90 ma 3 power supply current: standby i sbt1 50 45 40 35 30 ma i sbc2 25 25 25 25 25 ma power supply current: operating parameter ce\ > (v cc -0.2); v cc = max all other inputs < 0.2v or > (v cc - 0.2v), f = 0 hz ce\ > v ih ; v cc = max f = 0 hz max conditions ce\ < v il ; v cc = max output open description conditions sym max units notes input capacitance c i 8pf 4 output capacitance c o 10 pf 4 t a = 25 o c, f = 1mhz vcc = 5v
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 electrical characteristics and recommended ac operating conditions (note 5) (-55 o c < t c < 125 o c; v cc = 5v +10%) min max min max min max min max min max read cycle read cycle time t rc 12 15 20 25 35 ns address access time t aa 12 15 20 25 35 ns chip enable access time t ace 12 15 20 25 35 ns output hold from address change t oh 22222 ns chip enable to output in low-z t lzce 22222 ns7 chip disable to output in high-z t hzce 7 8 10 12 15 ns 6, 7 chip enable to power-up time t pu 00000 ns chip disable to power-down time t pd 12 15 20 25 35 ns output enable access time t aoe 6 7 8 10 15 ns output enable to output in low-z t lzoe 00008 ns output disable to output in high-z t hzoe 6 7 8 10 15 ns 6 write cycle write cycle time t wc 12 15 20 25 35 ns chip enable to end of write t cw 10 12 15 20 25 ns address valid to end of write t aw 10 12 15 20 25 ns address setup time t as 00000 ns address hold from end of write t ah 00000 ns write pulse width t wp 10 12 15 20 25 ns data setup time t ds 7 8 10 12 15 ns data hold time t dh 00000 ns write disable to output in low-z t lzwe 22222 ns7 write enable to output in high-z t hzwe 060708010015ns 6, 7 notes description -12 symbol units -35 -25 -20 -15
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 ac test conditions input pulse levels ...................................... vss to 3.0v input rise and fall times ......................................... 5ns input timing reference levels ................................ 1.5v output reference levels ....................................... 1.5v output load ................................. see figures 1 and 2 notes 1. all voltages referenced to v ss (gnd). 2. -3v for pulse width < 20ns 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs unloaded, and f = 1 hz. t rc (min) 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t hzce , t hzoe and t hzwe are specified with cl = 5pf as in fig. 2. transition is measured 200mv typical from steady state voltage, allowing for actual tester rc time constant. 7. at any given temperature and voltage condition, t hzce is less than t lzce , and t hzwe is less than t lzwe . 8. we\ is high for read cycle. 9. device is continuously selected. chip enables and output enables are held in their active state. 10. address valid prior to, or coincident with, latest occurring chip enable. 11. t rc = read cycle time. 12. ce2 timing is the same as ce1\ timing. the waveform is inverted. fig. 1 output load equivalent fig. 2 output load equivalent data retention electrical characteristics (l version only) 123 1 2 3 1 2 3 123 1 23 4 1 23 4 1 23 4 1234 dont care undefined low vcc data retention waveform 12345678 12345678 12345678 12345678 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 123456789 123456789 123456789 123456789 123 1 2 3 1 2 3 123 1234 1 23 4 1 23 4 1234 data retention mode v dr > 2v 4.5v 4.5v v dr t cdr t r v ih v il v cc ce\ description sym min max units notes v cc for retention data v dr 2 --- v data retention current ce\ > (v cc - 0.2v) v in > (v cc - 0.2v) or < 0.2v v cc = 2v i ccdr 1ma chip deselect to data retention time t cdr 0 --- ns 4 operation recovery time t r t rc ns 4, 11 conditions +5v q 255 30pf 480 5 pf +5v q 255 480
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 6 taa toh trc trc previous data valid valid data valid address dq read cycle no. 1 8, 9 t rc t aa t oh 1234 1 23 4 1234 1234 1 23 4 1 23 4 1234 dont care undefined tpd tpu thzce tace tlzce thzoe tlzoe taoe trc trc data valid ce\ oe\ dq icc read cycle no. 2 7, 8, 10 t rc t aoe t lzoe t hzoe t hzce t lzce t ace t pu t pd high-z
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 note: output enable (oe\) is inactive (high). write cycle no. 2 7, 12, 13 (write enabled controlled) 1234 1 23 4 1 23 4 1234 12345 1 234 5 1 234 5 12345 dont care undefined write cycle no. 1 12 (chip enabled controlled) tdh tds twp1 twp1 tah tcw taw tcw tas twc twc high z data vaild address ce\ we\ d q t wc t aw t as t cw t ah t wp t ds t dh 1234567890123456789012 1234567890123456789012 1 1 1 1 1 123456789012345678901234567890121234567890 123456789012345678901234567890121234567890 1 1 1 1 1 tdh twp1 twp1 tas taw tcw tah tcw twc twc data valid address ce\ we\ d q high-z t dh t ds t wc t aw t ah t cw t as t wp 12345678901234567 1 234567890123456 7 12345678901234567 12 12 12 1 1 1 1 12345678901234567890123 1 234567890123456789012 3 12345678901234567890123 12 1 1 1 1 123456789 123456789 123456789 dq dq q high-z q high-z
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 mechanical definitions* asi case #106 (package designator c) smd 5962-86859, case outline l note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. ea c d e min max a --- 0.200 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d --- 1.280 e 0.220 0.310 ea e l 0.125 0.200 q 0.015 0.060 s1 0.005 --- symbol 0.100 bsc smd specifications 0.300 bsc a q l e b b2 s1
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 * all measurements are in inches. mechanical definitions* asi case #204 (package designator ec) smd 5962-86859, case outline u note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. a a1 d3 min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 b2 d 0.342 0.358 d1 d2 d3 --- 0.358 e 0.540 0.560 e1 e2 e3 --- 0.558 e h l 0.045 0.055 l2 0.075 0.095 symbol smd specifications 0.072 ref 0.200 bsc 0.100 bsc 0.040 ref 0.050 bsc 0.200 bsc 0.400 bsc e d e3 hx45 o e1 l2 b1 d1 l e b2 e2 d2 h x 45 o
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 *available processes it = industrial temperature range -40 o c to +85 o c xt = extended temperature range -55 o c to +125 o c 883c = full military processing -55 o c to +125 o c ** options l = 2v data retention/low power ordering information device number package type speed ns options** process device number package type speed ns options** process mt5c6405 c -12 l /* mt5c6405 ec -12 l /* mt5c6405 c -15 l /* mt5c6405 ec -15 l /* mt5c6405 c -20 l /* mt5c6405 ec -20 l /* mt5c6405 c -25 l /* mt5c6405 ec -25 l /* mt5c6405 c -35 l /* mt5c6405 ec -35 l /* mt5c6405 c -45 l /* mt5c6405 ec -45 l /* mt5c6405 c -55 l /* mt5c6405 ec -55 l /* mt5c6405 c -70 l /* mt5c6405 ec -70 l /* example: mt5c6405c-25l/xt example: mt5c6405ec-15l/it
sram mt5c6405 austin semiconductor, inc. mt5c6405 rev. 2.0 5/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 asi to dscc part number cross reference* asi package designator c asi p ar t # smd p ar t # mt5c6805c-35/883c 5962-8685918la mt5c6805c-35l/883c 5962-8685917la mt5c6805c-45/883c 5962-8685916la mt5c6805c-45l/883c 5962-8685915la mt5c6805c-55/883c 5962-8685914la mt5c6805c-55l/883c 5962-8685913la mt5c6805c-70/883c 5962-8685912la mt5c6805c-70l/883c 5962-8685911la asi package designator ec asi part # smd part # mt5c6805ec-35/883c 5962-8685918ua mt5c6805ec-35l/883c 5962-8685917ua mt5c6805ec-45/883c 5962-8685916ua mt5c6805ec-45l/883c 5962-8685915ua mt5c6805ec-55/883c 5962-8685914ua mt5c6805ec-55l/883c 5962-8685913ua mt5c6805ec-70/883c 5962-8685912ua mt5c6805ec-70l/883c 5962-8685911ua * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd.

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